1. Field of the Invention
The present invention generally relates to a silicon structure and to a method of making the silicon structure, and more particularly to small complementary metal oxide semiconductor (CMOS) circuitry and a method of producing the small CMOS circuitry such as transistors, memories, etc. and integration of the same using a common substrate structure.
2. Description of the Related Art
Bonding of silicon dioxide and silicon has been practiced for many years. Several manufacturers supply wafers in which, in a desired step, two substrates are bonded together with silicon dioxide as the bonding layers.
For example, Lasky, "Wafer Bonding for Silicon-On-Insulator Technologies" Appl. Phys. Lett. 48 78(1986), described this procedure originally. Aspar et al., "Basic Mechanisms Involved in the Smart-Cut Process," Microelectronic Engineering 36 233(1997), describe the smart-cut process where a bonded wafer breaks off due to excess hydrogen. Sanchez et al., "Spontaneous Direct Bonding of Thick Silicon Nitride," J. Micromech. Microeng. 7 111 (1997), describe bonding with silicon nitride. Tong et al., "Silicon Carbide Wafer Bonding," J. Electrochem. Soc. 142 232(1995), describe bonding with silicon carbide. Goh et al., "Electrical Characterization of Dielectrically Isolated Silicon Substrates Containing Buried Metallic Layer," IEEE Electron Device Letters 18 232 (1997), describe use of WSi.sub.2 by using a poly-silicon capping of tungsten to bond to a silicon dioxide layer.
A problem of conventional techniques and structures is that, at small gate lengths, it becomes increasingly difficult to control the flow of electrons by the gate and independent of the drain voltage. Specifically, control of current close to the gated oxide/semiconductor interface is an increasingly difficult problem as gate lengths are reduced. Achieving good control requires an electrostatic potential barrier from the channel towards the substrate.
Such a potential barrier is typically produced by doping. However, such a procedure becomes difficult at small dimensions. Specifically, this higher doping in the substrate suffers from problems of random dopant distribution and control in placing of dopants.
Another method is to provide a back-plane which is separated from the conducting silicon by a barrier of an insulator. A back-plane of thick silicon with thick oxide is described by I. C. Yang et al., "Back-gated CMOS on FOIAS for Dynamic Threshold Voltage Control", Tech. Digest of IEDM, 1995. However, the conventional methods of providing a back-plane for such a purpose have been problematic. For example, the insulators are thick, the backplane silicon is thick, and the method of formation leaves hydrogen in the insulator which leads to memory effects following a high temperature anneal. Further, large voltages are required.